Low Stress Dielectric Layers for Wafer Level Packages to Reduce Wafer Warpage and Improve Board-Level Temperature-Cycle Reliability

Abstract

This paper presents a neg­a­tive-tone pho­toim­age­able spin-on dielec­tric mate­r­i­al that is based on a unique mol­e­cule for wafer lev­el pack­ag­ing appli­ca­tion. The mol­e­cule is an extend­ed poly­imide hav­ing pho­toac­tive maleimide end groups. It is an ide­al alter­na­tive to con­ven­tion­al dielec­tric mate­ri­als for solv­ing both the wafer warpage and tem­per­a­ture cycle RDL crack issues.

Introduction

The trend to big­ger wafer size and thin­ner wafer thick­ness is aggra­vat­ing wafer warpage due to resid­ual film stress from the poly­mer lay­ers on the wafer as shown in Fig. 1.

Con­ven­tion­al dielec­tric lay­ers used in wafer-lev­el pack­ag­ing are based on PBO/polyimides that are formed by way of a con­den­sa­tion reac­tion which requires a “hard bake” step at a tem­per­a­ture of 300°C.

Dur­ing this con­den­sa­tion reac­tion, new chem­i­cal bonds are formed as the mate­r­i­al crosslinks into a ther­moset poly­mer and the fugi­tive con­den­sate is dri­ven out of the coat­ing to result in high vol­ume shrink­age stress (Fig. 2).

As the ther­moset mate­r­i­al cools from “hard bake” tem­per­a­ture to room tem­per­a­ture, CTE mis­match between the ther­moset mate­r­i­al and sil­i­con induces strain over a large tem­per­a­ture range. This, cou­pled with the high mod­u­lus of the mate­r­i­al, results in high CTE mis­match stress on the wafer. The shrink­age and CTE mis­match stress pro­duce sig­nif­i­cant wafer warpage on thin and large diam­e­ter wafers.

On the oth­er hand, when a fin­ished wafer lev­el pack­age, such as a fan-out WLP, is sol­dered onto a PCB and sub­ject­ed to tem­per­a­ture cycling, the sol­der joints and dielec­tric lay­ers see CTE mis­match stress between the board and the sil­i­con. High mod­u­lus con­ven­tion­al dielec­tric lay­ers are poor stress absorbers. With stan­dard SAC sol­der ball, the cyclic stress man­i­fests itself in fatigue crack­ing of the sol­der. With new sol­der alloy with improved met­al­lur­gi­cal prop­er­ties, how­ev­er, the fail­ure mode is shift­ed to “crack in RDL dielec­tric layers”.

In addi­tion, the dielec­tric con­stants and dielec­tric dis­si­pa­tion of con­ven­tion­al PI/PBO are rel­a­tive­ly high in the low k world. This is a lim­it­ing fac­tor for high-fre­quen­cy applications.

Molecular level approach

To resolve the above-men­tioned prob­lems, a unique imide- extend­ed liq­uid bis maleimide monomer as shown in the block dia­gram in Fig. 3 was prepared.

Like con­ven­tion­al poly­imides, the mol­e­cule uses dian­hy­drides and diamines to pro­duce the back­bone; except the amic acid-to-poly­imide con­ver­sion is per­formed in a reac­tor and the water con­den­sa­tion is extract­ed. This elim­i­nates the need for the high-tem­per­a­ture hard bake step and high vol­ume shrink­age dur­ing cure from the end-user process. Essen­tial­ly, it removes the stress­es asso­ci­at­ed with the high-tem­per­a­ture hard bake and vol­ume shrink­age. The Gen­er­al­ized reac­tion mech­a­nism of the con­ven­tion­al aro­mat­ic Poly­imide Formation
imide func­tion­al group is one of the most ther­mal­ly sta­ble groups known. Thus, the monomer pro­vides a maleimide func­tion­al­ized ther­moset com­po­si­tion with­out com­pro­mis­ing supe­ri­or ther­mal stability.

By chang­ing the anhy­dride and amine start­ing mate­ri­als, a wide vari­ety of prop­er­ties, liq­uids, rub­ber-like films, and stiff glassy solids, can be prepared.

For RDL dielec­tric appli­ca­tion, an aliphat­ic back­bone monomer is cho­sen to yield a low mod­u­lus, low Dk/Df, and hydropho­bic mate­r­i­al when cured. The for­mu­lat­ed mate­r­i­al is UV cur­able, pho­toim­age­able, and can be processed using stan­dard wafer coat­ing meth­ods as shown in Fig. 4.

The sur­face is non-tacky after spin coat­ing and dry­ing. Imag­ing is a neg­a­tive tone and requires 500 mJ/cm2. Crosslink­ing of the pho­toim­age­able monomer occurs when the coat­ing is exposed to UV I‑line which ini­ti­ates a chain reac­tion that prop­a­gates through the addi­tion of chem­i­cal bonds between the pho­toac­tive maleimide end groups. No high tem­per­a­ture “hard bake” is required. The final step is a “post devel­op bake” at 125°C to 175°C to remove any remain­ing sol­vents and to pro­mote bond­ing of cou­pling agents for bet­ter adhesion.

Fig. 5 shows expo­sure of 500 mJ/cm2 pro­vides suf­fi­cient cross-link­ing to achieve >80% thickness.

Fig. 6 shows the unex­posed mate­r­i­al can be eas­i­ly washed away by the devel­op­ing solvent.

Fig. 7 shows an exam­ple of via holes with an aspect ratio of 0.5 (20 μm diam­e­ter, 10 μm thick­ness) on SiN pas­si­va­tion. With fur­ther opti­miza­tion in for­mu­la­tion and equip­ment set­up, the aspect ratio of 2.0 (5 μm diam­e­ter, 10 μm thick­ness) has been reported.

As shown in Fig. 8, the over­all cure shrink­age is very low com­pared to con­ven­tion­al mate­ri­als. This is because the back­bone of the oligomer is ful­ly imidized and no fur­ther con­den­sa­tion is required dur­ing processing.

The aliphat­ic back­bone yields a low mod­u­lus mate­r­i­al. As shown in Table 1, the mate­r­i­al has less than one-tenth mod­u­lus of con­ven­tion­al PBO and PI resins.

Once cured, the mate­r­i­al con­tains only ther­mal­ly sta­ble imide moi­eties which have sim­i­lar ther­mal sta­bil­i­ty and decom­po­si­tion tem­per­a­ture com­pared to con­ven­tion­al poly­imide as shown in Fig. 9.

Dur­ing pho­topoly­mer­iza­tion, the BMI func­tion­al units cross-link to become a ful­ly cured ther­moset. No volatiles are gen­er­at­ed on the cure. The cured mate­r­i­al is ther­mal­ly sta­ble at 150°C high-tem­per­a­ture stor­age. As shown in Fig. 10, the mod­u­lus of the cured film remains sta­ble over 1000 hours.

Free-rad­i­cal cure poly­mer­iza­tion allows a wide range of cou­pling agents to be used. By select­ing the appro­pri­ate cou­pling agents, excel­lent adhe­sion is obtained on sil­i­con and cop­per before and after 96 hours of 121°C pres­sure cook­er as mea­sured using the cross-cut adhe­sion tests fol­low­ing the ISO 2409 method in Fig. 11.

With its hydropho­bic back­bone, the imide-linked BMI has low mois­ture uptake. As shown in Fig. 12, it per­forms very well in 1000 hour of 85°C /85%RH elec­tri­cal migration.

Table 2 lists the mate­r­i­al prop­er­ties. As shown, it is a low mod­u­lus (260 MPa) mate­r­i­al. It has the high ther­mal sta­bil­i­ty (5% weight loss at 428°C) of con­ven­tion­al mate­ri­als but with the advan­tage of bet­ter high-fre­quen­cy elec­tri­cal per­for­mance in terms of much low­er Dk and Df, and bet­ter leak­age cur­rent and elec­tro-migra­tion in terms of much low­er water absorption.

Wafer Warpage

Wafer warpage due to film stress can be explained by

Stoney equa­tion:

r= E_s  * T_s²/ (1‑v) * 6*σ_f *T_f

where

r = radius of cur­va­ture of the wafer

Es = Elas­tic Mod­u­lus of silicon,

ts = thick­ness of the wafer

v = Pois­son’s ratio of silicon,

tf = thick­ness of film

σf = film stress =Ef*εf where

Ef = Elas­tic Mod­u­lus of film

εf = film strain

1. For strain due to CTE mismatch

εf=(αf-αs) ΔT

where

αf = CTE of film,

αs = CTE of silicon,

ΔT= tem­per­a­ture difference

2. For strain due to Cure shrinkage

εf=ΔV

where

ΔV= vol­ume shrinkage

UV cur­ing at near room-tem­per­a­ture results in a much small­er cool­ing tem­per­a­ture excur­sion. As such, the ΔT term in the equa­tion above is small com­pared to the large tem­per­a­ture excur­sion between cur­ing at 350°C and test­ing warpage at 25°C. Fur­ther­more, since cure shrink­age from the free rad­i­cal poly­mer­iza­tion of BMI is much small­er than from con­den­sa­tion cure, the ΔV term is also small. The over­all film strain εf from UV cur­ing of imide-linked BMI is small and hence the film stress σf is much less than con­ven­tion­al PIs. Since σf is in the denom­i­na­tor of the Radius of Cur­va­ture equa­tion, it fol­lows that the radius of cur­va­ture is large and wafer warpage is sig­nif­i­cant­ly low­er than that of con­ven­tion­al wafer coat­ing materials.

As shown in Fig. 13, 200 mm wafers were used for wafer warpage comparison.

One wafer was coat­ed with low- tem­per­a­ture cure con­ven­tion­al mate­r­i­al and cured at 200°C fol­lowed by PDD at 175°C. Cured film thick­ness was around 10 μm. Both wafers were thinned to 50 μm using the same back grind­ing con­di­tions, DISCO DGP8761, #320  #2000  Dry pol­ish. The 200°C cure mate­r­i­al reg­is­tered 19 mm of warpage while the BMI wafer was almost flat.

Stress Buffering

As a low mod­u­lus mate­r­i­al, the imide-linked BMI improves reli­a­bil­i­ty through self-defor­ma­tion there­by act­ing as a stress buffer lay­er. The defor­ma­tion of the dielec­tric lay­ers absorbs cyclic stress dur­ing board-lev­el tem­per­a­ture cycle test and mechan­i­cal shock dur­ing drop test to extend sol­der joint life.

To demon­strate the stress buffer­ing effect of the low mod­u­lus mate­r­i­al, stress buffer lay­ers of dif­fer­ent thick­ness­es were added to a BSI CMOS sen­sor CSP [1]. The CSPs were tem­per­a­ture cycles. Fig. 14 shows the inclu­sion of the stress buffer at where sol­dered bump will be placed.

Fig. 15 shows the aver­age resis­tance mea­sure­ments dur­ing board-lev­el tem­per­a­ture cycling.

As shown, the ref­er­ence leg that was with­out any stress buffer lay­er, start­ed to reg­is­ter an increase in aver­age resis­tance before 1000 cycles. The three legs with 5μm, 10μm, and 15μm stress buffer lay­er showed no sig­nif­i­cant increase.

Fig. 16 is a con­tin­u­a­tion of the tem­per­a­ture cycle test with an ampli­fied Y axis. As shown, the 5μm start­ed show­ing an increase in resis­tance after 4000 cycles, while the thick­er buffer lay­er legs con­tin­ued to show low resis­tance even up to 6000 cycles.

Fig. 17 is a log-log plot on the fail­ure rate. The sol­der bump life was esti­mat­ed to be 4000 cycles with just 5 μm of a stress buffer layer.

Other Applications

As men­tioned pre­vi­ous­ly in the mol­e­c­u­lar design sec­tion, a wide vari­ety of imide-linked BMI can be pre­pared with dif­fer­ent prop­er­ties by chang­ing the anhy­dride and amine start­ing mate­ri­als. The mol­e­cule in Fig. 3 can also be designed to have very low CTE, while main­tain­ing the low Dk and Df advan­tages. Table 3 shows the prop­er­ties of one such molecule.

By dis­solv­ing in a sol­vent, adding ther­mal ini­tia­tor and addi­tives, this mol­e­cule can be for­mu­lat­ed into a filler-free, 175°C ther­mal cure, low CTE mate­r­i­al suit­able for poly­mer col­lar type of appli­ca­tions to improve drop test per­for­mance [2]. Com­pared to epoxy-based poly­mer col­lars, the BMI offers high ther­mal sta­bil­i­ty, low Dk/Df and low mois­ture absorption.

Conclusion

Maleimide-ter­mi­nat­ed aliphat­ic poly­imide has key pro­cess­ing and per­for­mance advan­tages over con­ven­tion­al wafer coat­ing mate­ri­als while main­tain­ing the high ther­mal sta­bil­i­ty and excel­lent chem­i­cal resis­tance of con­ven­tion­al mate­ri­als. The UV cure capa­bil­i­ty allows the low­est pos­si­ble wafer warpage at room tem­per­a­ture. “Post devel­op­ment dry” to dri­ving out resid­ual sol­vent and improve bond­ing of cou­pling agents can be done at the tem­per­a­ture from 125°C to 175°C. The low mod­u­lus prop­er­ty of aliphat­ic back­bone is ben­e­fi­cial in mak­ing an RDL dielec­tric lay­er, dou­bling up as a stress buffer lay­er to extend sol­der life and delay crack ini­ti­a­tion. Its excel­lent dielec­tric prop­er­ties (Dk = 2.45, Df =0.001) are ben­e­fi­cial for high fre­quen­cy WLP.

Acknowledgments

The authors would like to thank ZyCube Co. for test­ing the mate­ri­als; espe­cial­ly to Hiro­fu­mi Naka­mu­ra san for pro­vid­ing the tem­per­a­ture cycling results and his advice on the inter­pre­ta­tion of the test data.

References

1. Naka­mu­ra, H., “Using three-dimen­sion­al pack­ag­ing tech­nol­o­gy for auto­mo­tive image sen­sor CSP,” 2196th Elec­tron­ic Jour­nal, Tech­ni­cal Sem­i­nar, Japan, Apr. 2014.
2. D Bhupin­der Singh, Vanes­sa Smet, Jae­sik Lee, Gary Menezes, Mako­to Kobayashi, Pulugurtha Markondeya Raj, Venky Sun­daram, Bri­an Rogge­man, Urmi Ray, Riko Rado­j­cic, Rao Tum­mala, “First Demon­stra­tion of Drop- test Reli­a­bil­i­ty of Ultra-thin Glass BGA Pack­ages Direct­ly Assem­bled on Boards for Smart­phone Appli­ca­tions,” 65th IEEE Elec­tron­ic Com­po­nents & Tech­nol­o­gy Con­fer­ence, 2015, pp. 1566–1573.

To know more regard­ing Low-Stress Dielec­tric Lay­ers for Wafer Lev­el Pack­ages, vis­it www.caplinq.com. You can also con­tact us if you any queries regard­ing CAPLIN­Q’s adhe­sive, seal­ings, and coat­ings.