Dr. H. W. Rauhut
Research Scientist, Dexter Electronic Materials Division
Technical Paper, March 1992
For about thirty years, electronic device encapsulation has been the charter of epoxy molding compounds. First, epoxy packages embedded transistors, then DIP ICs, later VLSI ICs, SOICs, PLCCs, and now TSOPs and high-pin QFPs. There is an ongoing proliferation of device and package types, of which only a partial listing is shown below. High-performance ICs exhibit high speed and shrinking device features on larger semiconductor dies in smaller and thinner packages, as reflected in references (1), (2) and (3). The level of integration continues to increase in VLSI and microprocessor units. Plastic packaging has become more complex. Driving forces include automation, automobile applications and powerful, portable computer designs. An example of our growing dependence on microelectronic devices is shown by the automotive industry in Figure 1. Surface mount technology is the way of the future (Figure 2). Many modern electronic applications are also cost-driven. Semiconductor epoxy molding compounds have followed all these demanding developments, as they are an integral part of high technology. This paper describes and illustrates the evolution of microelectronic grade epoxies, their past, their present and their future (where discernible). Included are key areas of new development and methodology.
PACKAGE EVOLUTION TOWARDS LOWER CTEs
The first microelectronic powders, i.e., crystalline silica-filled, anhydride cured Bis‑A type epoxies, exhibited low glass transition temperatures and high coefficients of thermal expansion (Figures 3 & 4). Both properties were significantly improved around 1968, through (FS) fused silica-filled systems based on ECN (Epoxy Cresolic Novolac) resins and phenolic novolac hardeners. Further details on compound compositions were described earlier (4).
ECN became the workhorse resin, with typical TGs of 150–175°C (Figure 3). At present, industry debates the merits of both lower and higher glass transition temperature (Tg) and pursues both, dependent on the application. In the CTE area, epoxies are following a path of steadily decreasing thermal expansion (Figure 4), mainly through increasing their FS level, a logical development in view of package low-stress requirements.
Both resin and filler technology, including the introduction of spherical FS and a trend towards finer filler particles, have contributed to increased package performance (Figure 5). Consequently, shrinkage is decreasing (Figure 6).
STRESS REDUCTION, A CONTINUOUS CHALLENGE
The evolution of memory devices (including 4–16 Megabits), SOICs, QFPs and many other packages, requires steadily decreasing package stress. One can calculate the compressive stress of epoxy packages using CTE / modulus data from Thermal or Dynamic Mechanical Analyses and the following formula:
In these terms, the current low-stress status and trend are reflected in Figure 7. As discussed before, low-stress is associated with improved thermal cycle and thermal shock performance (5). Consequently, these epoxy properties show increasing trends (Figures 8–10).
With experimental materials, the future has already begun, as shown in a comparison of Figures 10 and 11. Such severe T‑shock testing does not only demonstrate low-stress, but also toughness, a desirable feature of plastic packages with reduced size and thickness.
Figure 12 contains a calculated stress framework, in which data from various compounds is inserted. Evidently, the industry uses a wide range of CTEs and moduli for similar low package stress. Ideally, lowest CTEs and moduli should be combined. However, natural limits are set, since CTEs and moduli move into opposite directions in high-filler systems. Lowest stress DEM compounds benefit from either relatively low moduli or very low CTEs (Figures 12–13).
At present, the industry debates whether low-TG or high-TG approaches should be taken in low-stress compounds. As shown in Table 1, advantages and disadvantages are associated with each position, and a clear trend has not yet emerged. The author has experienced low-stress compounds with TGs from about 120° to 200°C. It appears that pragmatism prevails, dependent on the best results for a given device type.
Certain devices may generate a significant amount of Joule’s heat. In such cases, heat sinks are employed, but increased thermal conductivity through the plastic package is also desirable (6). Low-stress features were combined with high thermal conductivity for SiC packages and high power applications. Thermal conductivity increases in epoxies over the last twenty-five years are illustrated in Figure 14.
ANTI-POPCORN, A CRITICAL REQUIREMENT
On printed wiring boards, SMT is rapidly replacing through-hole technology (Figure 2). Small amounts of absorbed moisture in ICs may cause a popcorn phenomenon during vapor-phase reflow soldering, as high-boiling (215 °C) fluorocarbon fluid quickly vaporizes the moisture in the IC package and exerts pressure. Especially thin packages with large dies are vulnerable, since the force IC is exerted on the not only proportional to water vapor pressure, but also to the square of (L/T). L = IC pad Length; T = smallest IC Thickness.
Details on temperature/moisture exposure prior to popcorn testing may vary. Zero failures also depend on the device type (Figure 15). Encapsulant adhesion to the silicon chip has been identified as an anti-popcorn factor. As shown in our C‑SAM study, reduced wax amounts help improve chip adhesion (Table 2). However, some wax is needed for epoxy moldability in production, an example of a trade-off situation.
Another anti-popcorn factor, just recently demonstrated, is package toughness together with low-stress, as reflected by accelerated T‑shock testing in Figure 16. The best performing system shows zero solder dip failures using indented PLCCs. Besides toughness, reduced stress concentrations in the plastic package are helpful.
High hot flexural strength is another important factor to control package cracking during vapor-phase soldering, as shown by a series of DEM compounds in Figure 17. For moisture absorption, we usually employ pressure cooker (15 psi steam) exposure, rather than 85°C/85%RH conditions with much lower absorption (Figure 18). Whatever the condition, anti-popcorn remains an industry-wide challenge.
PURE RAW MATERIALS FOR PERFORMANCE
The selection of pure raw materials for epoxies is important for enhanced moisture performance. Ever finer and thinner aluminization patterns on highly integrated silicon chips can be quickly corroded in the presence of ionic impurities. Impurities in epoxies and their raw materials are now significantly lower than twenty years ago (Figure 19–22). Aluminum corrosion is also controlled by water extract conductivity and hydrogen ion concentration (pH). Since mobile ions, such as Cl– and Na+, are particularly harmful, their levels have been much reduced (Figure 21–22).
IMPROVED HUMIDITY-TEMPERATURE RELIABILITY
Advanced microelectronic devices have become increasingly more sensitive in Humidity-Temperature tests with Bias (HTB) and without. In addition, more demanding device tests and reliability evolved over the years. Highly Accelerated Temperature and Humidity Stress Test (HAST) techniques were developed (7). Consequently, microelectronic encapsulation powders do not only require pure raw materials, but also well balanced formulations and suitable manufacturing processes. Designed experimentation has been employed to identify suitable means for such challenges, including research on corrosion inhibitors and ion scavengers. An example of an epoxy with improved reliability is shown.
Molding compounds and their processing conditions include numerous, occasionally interacting factors, which are efficiently researched by designed experimentation. In classical experimentation, a balance of all factors is usually missing; bias and random failure are ignored. Designed experimentation identifies the significance or insignificance of each factor, and may point out factor interactions. Data interpretation by statistical means can be done manually (8,9), but computer software simplifies the task.
IMPORTANCE OF MOLDABILITY
With emphasis on high performance, epoxies must also aid, not hinder package manufacturing. Conventional, multi-cavity transfer molding has become less productive and uniform in quality than automatic molding (in 1–4 cavities with multi-plungers). Speed of cure, hot strength and release without premature cavity staining are important moldability issues. With time progressing, the number of non-staining shots is increasing. Also considered are the effects of molding on IC features inside of devices, such as paddle shift and wire sweep. Designed experimentation has been successfully used to identify composition factors and molding parameters that control wire sweep (Figure 23).
MEMORY DEVICES REQUIRE LOW ALPHA EMISSION
Random soft error adversely affects 256K RAM and megabit devices (10). Therefore, low-alpha epoxies with very low uranium (U) and thorium (Th) contamination are needed as encapsulants. Typical requirements call for <0.5 ppb U, and synthetic fused silicas have to be employed as fillers. Low-alpha epoxies are only briefly mentioned here, since they were recently described (11). The evolution of alpha emission in DEM epoxy compounds is shown in Figure 24.
Epoxy molding compounds have become sophisticated microelectronic encapsulants since their humble beginnings thirty years ago. Key performance properties and moldability have significantly changed in order to meet the challenges of a great variety of devices, including automold applications. Thin, large-chip epoxy packages require anti-popcorn performance and very low stress. Moisture reliability is more demanding, and epoxies for megabit memory devices must feature low alpha radiation. This paper reflects the current status, methodology, new development of semiconductor grade epoxies and some property projections into the near future.
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RETEC 1990, pp. 240–248; SPE Thermoset RETEC 1983 and 1984.
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LISTING OF ABBREVIATIONS
|Abbreviation||Full Form||Abbreviation||Full Form|
|CHIP||Section (die) of semiconductor wafer for ICs||DIP||Dual In-line Package|
|CMOS||Complementary Metal-Oxide Semiconductor / Logic IC||DRAM||Dynamic Random-Access Memory|
|COB||Chip on Board||IC||Integrated Circuit|
|DIE||Section (chip) of semiconductor wafer for ICs||HAST||Highly Accelerated Stress Testing (Temp / Moist)|
|MNOS||Metal Nitride Oxide Semiconductor||MCM||Multi-Chip Modules|
|MOS||Metal Oxide Semiconductor||NMOS||Negative Metal Oxide Semiconductor|
|PGA||Pin-Grid Array||PLCC||Plastic Leaded Chip Carrier / Leaded Quad Package|
|PMOS||Positive Metal Oxide Semiconductor||PWB||Printed Wiring Board|
|QFP||Quad Flat Pack||RAM||Random-Access Memory|
|S/C||Semiconductor||SMT||Surface Mount Technology|
|SOIC||Small Outline Integrated Circuit||SQFP||Shrink Quad Flat Pack|
|TAB||Tape Automated Bonding (ICs)||TSOP||Thin Small Outline Package|
|VLSI||Very Large-Scale Integration (ICs)|