advances in epoxy molding compounds

Advances in Epoxy Molding Compounds — Dexter Technical Paper (1992)

Dr. H. W. Rauhut

Research Sci­en­tist, Dex­ter Elec­tron­ic Mate­ri­als Division

Tech­ni­cal Paper, March 1992


For about thir­ty years, elec­tron­ic device encap­su­la­tion has been the char­ter of epoxy mold­ing com­pounds. First, epoxy pack­ages embed­ded tran­sis­tors, then DIP ICs, lat­er VLSI ICs, SOICs, PLCCs, and now TSOPs and high-pin QFPs. There is an ongo­ing pro­lif­er­a­tion of device and pack­age types, of which only a par­tial list­ing is shown below. High-per­for­mance ICs exhib­it high speed and shrink­ing device fea­tures on larg­er semi­con­duc­tor dies in small­er and thin­ner pack­ages, as reflect­ed in ref­er­ences (1), (2) and (3). The lev­el of inte­gra­tion con­tin­ues to increase in VLSI and micro­proces­sor units. Plas­tic pack­ag­ing has become more com­plex. Dri­ving forces include automa­tion, auto­mo­bile appli­cations and pow­er­ful, portable com­put­er designs. An exam­ple of our grow­ing depen­dence on micro­elec­tron­ic devices is shown by the auto­mo­tive indus­try in Fig­ure 1. Sur­face mount tech­nol­o­gy is the way of the future (Fig­ure 2). Many mod­ern elec­tron­ic appli­ca­tions are also cost-dri­ven. Semi­con­duc­tor epoxy mold­ing com­pounds have fol­lowed all these demand­ing devel­op­ments, as they are an inte­gral part of high tech­nol­o­gy. This paper describes and illus­trates the evo­lu­tion of micro­elec­tron­ic grade epox­ies, their past, their present and their future (where dis­cernible). Includ­ed are key areas of new devel­op­ment and methodology.

Electronic content per car
Market share of through-hole vs. surface-mount ICs


The first micro­elec­tron­ic pow­ders, i.e., crys­talline sil­i­ca-filled, anhy­dride cured Bis‑A type epox­ies, exhib­it­ed low glass tran­si­tion tem­per­a­tures and high coef­fi­cients of ther­mal expan­sion (Fig­ures 3 & ­4). Both prop­er­ties were signi­ficantly improved around 1968, through (FS) fused sil­i­ca-filled sys­tems based on ECN (Epoxy Creso­lic Novolac) resins and phe­no­lic novolac hard­en­ers. Fur­ther details on com­pound com­po­si­tions were described ear­li­er (4).

Evolution of Tg  of epoxy packages

ECN became the work­horse resin, with typ­i­cal TGs of 150–175°C (Fig­ure 3). At present, indus­try debates the mer­its of both low­er and high­er glass tran­si­tion tem­per­a­ture (Tg) and pur­sues both, depen­dent on the appli­ca­tion. In the CTE area, epox­ies are fol­low­ing a path of steadi­ly decreas­ing ther­mal expan­sion (Fig­ure 4), main­ly through increas­ing their FS lev­el, a log­i­cal devel­op­ment in view of pack­age low-stress requirements. 

Evolution of CTEs and Filler Levels of Epoxy IC Packages

Both resin and filler tech­nol­o­gy, includ­ing the intro­duc­tion of spher­i­cal FS and a trend towards fin­er filler par­ti­cles, have contri­buted to increased pack­age per­for­mance (Fig­ure 5). Conse­quently, shrink­age is decreas­ing (Fig­ure 6).

Upper limit of fused silica particle fillers
Shrinkage in semiconductor-grade epoxy compounds


The evo­lu­tion of mem­o­ry devices (includ­ing 4–16 Megabits), SOICs, QFPs and many oth­er pack­ages, requires steadi­ly decreas­ing pack­age stress. One can cal­cu­late the com­pres­sive stress of epoxy pack­ages using CTE / mod­u­lus data from Ther­mal or Dynam­ic Mechan­i­cal Analy­ses and the fol­low­ing formula:

Formula for compressive stress

In these terms, the cur­rent low-stress sta­tus and trend are reflect­ed in Fig­ure 7. As dis­cussed before, low-stress is asso­ci­at­ed with improved ther­mal cycle and ther­mal shock per­for­mance (5). Con­se­quent­ly, these epoxy prop­er­ties show increas­ing trends (Fig­ures 8–10).

Evolution of low-stress epoxies calculated compressive stress
Temperature cycling (–65/+150 °C/Air-to-Air) requirements for zero failures

With exper­i­men­tal mate­ri­als, the future has already begun, as shown in a com­par­i­son of Fig­ures 10 and 11. Such severe T‑shock test­ing does not only demon­strate low-stress, but also tough­ness, a desir­able fea­ture of plas­tic pack­ages with reduced size and thickness.

Thermal shock (–65/+150 °C/Air-to-Air) requirements for zero failures
Accelerated T-shock testing (–196/+260 °C)
T-shock performance (–196/+260 °C)

Fig­ure 12 con­tains a cal­cu­lat­ed stress frame­work, in which data from var­i­ous com­pounds is insert­ed. Evi­dent­ly, the indus­try uses a wide range of CTEs and mod­uli for sim­i­lar low pack­age stress. Ide­al­ly, low­est CTEs and mod­uli should be com­bined. How­ev­er, nat­ur­al lim­its are set, since CTEs and mod­uli move into oppo­site direc­tions in high-filler sys­tems. Low­est stress DEM com­pounds ben­e­fit from either rel­a­tive­ly low mod­uli or very low CTEs (Fig­ures 12–13).

Compressive stress vs. CTE
CTE of DEM epoxies

At present, the indus­try debates whether low-TG or high-TG approach­es should be tak­en in low-stress com­pounds. As shown in Table 1, advan­tages and dis­ad­van­tages are asso­ci­at­ed with each posi­tion, and a clear trend has not yet emerged. The author has expe­ri­enced low-stress com­pounds with TGs from about 120° to 200°C. It appears that prag­ma­tism pre­vails, depen­dent on the best results for a giv­en device type.

Advantages and disadvantages of low stress approaches

Cer­tain devices may gen­er­ate a sig­nif­i­cant amount of Joule’s heat. In such cas­es, heat sinks are employed, but increased ther­mal con­duc­tiv­i­ty through the plas­tic pack­age is also desir­able (6). Low-stress fea­tures were com­bined with high ther­mal con­duc­tiv­i­ty for SiC pack­ages and high pow­er appli­ca­tions. Ther­mal con­duc­tiv­i­ty increas­es in epox­ies over the last twen­ty-five years are illus­trat­ed in Fig­ure 14.

Maximum thermal conductivity requirements for special applications


On print­ed wiring boards, SMT is rapid­ly replac­ing through-hole tech­nol­o­gy (Fig­ure 2). Small amounts of absorbed mois­ture in ICs may cause a pop­corn phe­nom­e­non dur­ing vapor-phase reflow sol­der­ing, as high-boil­ing (215 °C) flu­o­ro­car­bon flu­id quick­ly vapor­izes the mois­ture in the IC pack­age and exerts pres­sure. Espe­cial­ly thin pack­ages with large dies are vul­ner­a­ble, since the force IC is exert­ed on the not only pro­por­tion­al to water vapor pres­sure, but also to the square of (L/T). L = IC pad Length; T = small­est IC Thickness.

Details on temperature/moisture expo­sure pri­or to pop­corn test­ing may vary. Zero fail­ures also depend on the device type (Fig­ure 15). Encap­su­lant adhe­sion to the sil­i­con chip has been iden­ti­fied as an anti-pop­corn fac­tor. As shown in our C‑SAM study, reduced wax amounts help improve chip adhe­sion (Table 2). How­ev­er, some wax is need­ed for epoxy mold­abil­i­ty in pro­duc­tion, an exam­ple of a trade-off situation.

Anoth­er anti-pop­corn fac­tor, just recent­ly demon­strat­ed, is pack­age tough­ness togeth­er with low-stress, as reflect­ed by accel­er­at­ed T‑shock test­ing in Fig­ure 16. The best per­form­ing sys­tem shows zero sol­der dip fail­ures using indent­ed PLCCs. Besides tough­ness, reduced stress concen­trations in the plas­tic pack­age are helpful.

Anti-popcorn evolution (IC exposure to 85 °C/ 85% RH)
Moist PLCC solder dips @ 215 °C vs. T-shock performance
Wax Level vs. C-SAM adhesion of 230 × 230 mils die after vapor phase treatment

High hot flex­ur­al strength is anoth­er impor­tant fac­tor to con­trol pack­age crack­ing dur­ing vapor-phase sol­der­ing, as shown by a series of DEM com­pounds in Fig­ure 17. For mois­ture absorp­tion, we usu­al­ly employ pres­sure cook­er (15 psi steam) expo­sure, rather than 85°C/85%RH condi­tions with much low­er absorp­tion (Fig­ure 18). What­ev­er the con­di­tion, anti-pop­corn remains an indus­try-wide challenge.

Vapor phase failures vs. hot flexural strength
MG60F Moisture Absorption


The selec­tion of pure raw mate­ri­als for epox­ies is impor­tant for enhanced mois­ture perform­ance. Ever fin­er and thin­ner alu­miniza­tion pat­terns on high­ly inte­grat­ed sil­i­con chips can be quick­ly cor­rod­ed in the pres­ence of ion­ic impu­ri­ties. Impu­ri­ties in epox­ies and their raw mate­ri­als are now sig­nif­i­cant­ly low­er than twen­ty years ago (Fig­ure 19–22). Alu­minum cor­ro­sion is also con­trolled by water extract con­duc­tiv­i­ty and hydro­gen ion con­cen­tra­tion (pH). Since mobile ions, such as Cl and Na+, are par­tic­u­lar­ly harm­ful, their lev­els have been much reduced (Fig­ure 21–22).

Water extract conductivity and pH of semiconductor grade epoxies
WEC, pH, and free-phenol content in Novolac hardeners
Hydrolyzable chloride in semiconductor-grade ECN resins
Sodium in semiconductor-grade ECN resins


Advanced micro­elec­tron­ic devices have become increas­ing­ly more sen­si­tive in Humid­i­ty-Tem­per­a­ture tests with Bias (HTB) and with­out. In addi­tion, more demand­ing device tests and reli­a­bil­i­ty evolved over the years. High­ly Accel­er­at­ed Tem­per­a­ture and Humid­i­ty Stress Test (HAST) tech­niques were devel­oped (7). Con­se­quent­ly, micro­elec­tron­ic encap­su­la­tion pow­ders do not only require pure raw mate­ri­als, but also well bal­anced formu­lations and suit­able man­u­fac­tur­ing process­es. Designed experimen­tation has been employed to iden­ti­fy suit­able means for such chal­lenges, includ­ing research on cor­ro­sion inhibitors and ion scav­engers. An exam­ple of an epoxy with improved reli­a­bil­i­ty is shown.


Mold­ing com­pounds and their pro­cess­ing con­di­tions include numer­ous, occa­sion­al­ly inter­acting fac­tors, which are effi­cient­ly researched by designed experi­mentation. In clas­si­cal experimen­tation, a bal­ance of all fac­tors is usu­al­ly miss­ing; bias and ran­dom fail­ure are ignored. Designed exper­i­men­ta­tion iden­ti­fies the sig­nif­i­cance or insignif­i­cance of each fac­tor, and may point out fac­tor inter­ac­tions. Data interpre­tation by sta­tis­ti­cal means can be done man­u­al­ly (8,9), but com­put­er soft­ware sim­pli­fies the task.


With empha­sis on high perform­ance, epox­ies must also aid, not hin­der pack­age man­u­fac­tur­ing. Con­ven­tion­al, mul­ti-cav­i­ty trans­fer mold­ing has become less produc­tive and uni­form in qual­i­ty than auto­mat­ic mold­ing (in 1–4 cav­i­ties with mul­ti-plungers). Speed of cure, hot strength and release with­out pre­ma­ture cav­i­ty stain­ing are impor­tant mold­abil­i­ty issues. With time pro­gress­ing, the num­ber of non-stain­ing shots is increas­ing. Also con­sid­ered are the effects of mold­ing on IC fea­tures inside of devices, such as pad­dle shift and wire sweep. Designed exper­i­men­ta­tion has been suc­cess­ful­ly used to iden­ti­fy com­po­si­tion fac­tors and mold­ing para­me­ters that con­trol wire sweep (Fig­ure 23).


Ran­dom soft error adverse­ly affects 256K RAM and megabit devices (10). There­fore, low-alpha epox­ies with very low ura­ni­um (U) and tho­ri­um (Th) con­t­a­m­i­na­tion are need­ed as encap­su­lants. Typ­i­cal require­ments call for <0.5 ppb U, and syn­thet­ic fused sil­i­cas have to be employed as fillers. Low-alpha epox­ies are only briefly men­tioned here, since they were recent­ly described (11). The evo­lu­tion of alpha emis­sion in DEM epoxy com­pounds is shown in Fig­ure 24.

Wire sweep vs. transfer molding conditions
Alpha emission of DEM compounds


Epoxy mold­ing com­pounds have become sophis­ti­cat­ed micro­elec­tron­ic encap­su­lants since their hum­ble begin­nings thir­ty years ago. Key per­for­mance prop­er­ties and mold­abil­i­ty have sig­nif­i­cant­ly changed in order to meet the chal­lenges of a great vari­ety of devices, includ­ing auto­mold appli­ca­tions. Thin, large-chip epoxy pack­ages require anti-pop­corn per­for­mance and very low stress. Mois­ture reli­a­bil­i­ty is more demand­ing, and epox­ies for megabit mem­o­ry devices must fea­ture low alpha radi­a­tion. This paper reflects the cur­rent sta­tus, method­ol­o­gy, new devel­op­ment of semi­con­duc­tor grade epox­ies and some prop­er­ty pro­jec­tions into the near future.

CAPLINQ spe­cial­izes in the dis­tri­b­u­tion and tech­ni­cal exper­tise of spe­cial­ty chem­i­cals and mate­ri­als, includ­ing but not lim­it­ed to ther­mal inter­face mate­ri­als, epoxy mold­ing com­pounds (EMCs) and coat­ing pow­ders, and adhe­sives. In par­tic­u­lar, CAPLINQ rep­re­sents EMCs from Hysol Huawei Elec­tron­ic Co. Ltd. in Europe, Amer­i­ca, and Asia while we also man­u­fac­ture our own line of prod­ucts.

You may find it use­ful to browse our over­all semi­con­duc­tor-grade epoxy mold­ing com­pounds prod­uct cat­a­log. We also have Die attach mate­ri­als, Ther­mal inter­face mate­ri­als, and Encap­su­la­tion mate­ri­als that can pro­vide solu­tions to you and your team. 

Please also refer to this CAPLINQ Prod­uct Port­fo­lio pre­sen­ta­tion for detailed infor­ma­tion about our prod­uct offerings.

Should there be addi­tion­al spec­i­fi­ca­tions required, please con­tact us to assist and pro­vide you with addi­tion­al recommendations.


  1. R. Scoff, “Pack­ag­ing High-Speed, High-Per­for­mance ICs”, Semi­con­duc­tor Inter­na­tion­al, August 1991, pp. 64–68.
  2. M. Cohen et al, “TSOP’s Make IC DRAM Cards Pos­si­ble With Con­ven­tion­al Tech­nol­o­gy”,
    Micro­elec­tron­ics Man­u­fac­tur­ing Tech­nol­o­gy, Sep­tem­ber 1991, pp. 19–20.
  3. P. Robock, “Plas­tic Pack­ag­ing Technology‑A User’s Perspec­tive”, IBM publication.
  4. H. Rauhut, “Epoxy Encap­sulants”, Ther­moset RETEC 1988, pp. 117–127.
  5. H. Rauhut, “Low-Stress Epoxy Encap­su­lants”, Ther­moset
    RETEC 1990, pp. 240–248; SPE Ther­moset RETEC 1983 and 1984.
  6. P. Proc­ter and J. Solc, “Improved Ther­mal Con­duc­tiv­i­ty in Micro­elec­tron­ic Encap­su­lants”, IEEE Pro­ceed­ings 1991, pp. 835842.
  7. J. Gunn et al, “High­ly Accel­erated Tem­per­a­ture and Humid­i­ty Stress Test Tech­nique (HAST)”, Reli­a­bil­i­ty Physics, 1981, IEEE cat­a­log No. 81CH1619‑6, pp. 4851.
  8. DuPont, Spe­cial­ty Ser­vices, “Strat­e­gy of Exper­i­men­ta­tion”, Revised Edi­tion, Octo­ber 1975.
  9. T. B. Bark­er, “Qual­i­ty by Exper­i­men­tal Design”, Mar­cel Dekker, Inc., New York, 1985.
  10. T. C. May et al, “Alpha­­Par­ti­cle-Induced Soft Errors in Dynam­ic Mem­o­ries”, Reli­a­bil­i­ty Physics Sym­po­sium, 1978, IEEE, Vol­ume ED-26, No. 1, 1979.
  11. H. Rauhut, “Low-Alpha Epoxy Mold­ing Com­pounds”, SPE ANTEC, Tech­ni­cal Papers Vol. XXXVII, 1991, pp. 1260–1264.


Abbre­vi­a­tionFull FormAbbre­vi­a­tionFull Form
CHIPSec­tion (die) of semi­con­duc­tor wafer for ICsDIPDual In-line Package
CMOSCom­ple­men­tary Met­al-Oxide Semi­con­duc­tor / Log­ic ICDRAMDynam­ic Ran­dom-Access Memory
COBChip on BoardICInte­grat­ed Circuit
DIESec­tion (chip) of semi­con­duc­tor wafer for ICsHASTHigh­ly Accel­er­at­ed Stress Test­ing (Temp / Moist)
MNOSMet­al Nitride Oxide SemiconductorMCMMul­ti-Chip Modules
MOSMet­al Oxide SemiconductorNMOSNeg­a­tive Met­al Oxide Semiconductor
PGAPin-Grid ArrayPLCCPlas­tic Lead­ed Chip Car­ri­er / Lead­ed Quad Package
PMOSPos­i­tive Met­al Oxide SemiconductorPWBPrint­ed Wiring Board
QFPQuad Flat PackRAMRan­dom-Access Memory
S/CSemi­con­duc­torSMTSur­face Mount Technology
SOICSmall Out­line Inte­grat­ed CircuitSQFPShrink Quad Flat Pack
TABTape Auto­mat­ed Bond­ing (ICs)TSOPThin Small Out­line Package
VLSIVery Large-Scale Inte­gra­tion (ICs)

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