Reliability testing

Material, Stress, Mechanical and Environmental induced mechanisms



After packaging and testing, encapsulated semiconductor devices must exhibit good reliability. Reliability is related to the probability at which packaged microelectronic systems will remain functional under realistic operating conditions for a given period of time.1 More often, accelerated test methods are performed to assess the field reliability of these devices because monitoring the performance and functionality of all device or package combinations seems to be nowhere near to possible.2 These accelerated reliability tests are performed to (1) elicit a certain failure mode rapidly, (2) identify package defects and possible failure sites and mechanisms, and (3) forecast the useful lifetime of the device based on acceleration factors. These tests are only effective if they induce problems that the devices might encounter under normal operating conditions.

Industry organizations set test standards that define which tests to perform and how to conduct them, ensuring that these tests accurately and consistently trigger failure modes across all industry suppliers. The initial standard, MIL-STD-883, was created to assess packaged electronic microsystems for military and aerospace purposes. Nevertheless, more recent standards were introduced because MIL-STD-883 was designed at a time when most packages were hermetic, meaning the chips were sealed within metallic cans or enclosed between ceramic substrates and caps. Currently, the Joint Electron Devices Engineering Council (JEDEC) establishes the standards for plastic semiconductor practices, with most of the reliability and qualification criteria falling under the JESD22 family of methods.3 Still, the testing methods stay mostly the same, but what's different are the conditions the packages are subjected to.

Common Reliability Tests




Test Conditions



Performed before other reliability tests to mimic the solder reflow conditions of surface mount packages

See Preconditioning

High-temperature storage


Elicit bond pad metallization failures by heating and halide reaction

1000 h at 150 or 175 °C

Temperature cycling


Induce thermal stress on the chip and the package

–65 °C to 150 °C for 1000 cycles in air

Thermal shock


Induce thermal stress on the chip and the package

–65 °C to 150 °C for 1000 cycles in liquid

Temperature humidity bias


Test the passivation integrity against ionic species under moisture and applied electrical bias

1000 h at 85 °C/ 85% RH 



Test the passivation integrity against ionic species under moisture

168 h or more at 121 °C and 15–30 psig

Highly accelerated temperature and humidity stress testing


Accelerated version of THB

110 °C or 130 °C under 85% RH and under vapor pressure for at least 96 h

Source: JEDEC, JEP150, Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components, May 2005, Table 1.3


1 Zhang, Hengyun Che, Faxing Lin, Tingyu Zhao, Wensheng. (2020). Modeling, Analysis, Design, and Tests for Electronics Packaging beyond Moore - 1.2.3 Stress and Reliability Issues. Elsevier. 

2 Chung, Henry Shu-hung Wang, Huai Blaabjerg, Frede Pecht, Michael. (2016). Reliability of Power Electronic Converter Systems - 4.1 Introduction. Institution of Engineering and Technology (The IET). 

3 Chen, A., & Lo, R.H.-Y. (2012). Semiconductor Packaging: Materials Interaction and Reliability (1st ed.). CRC Press.